NAND type flash memories are widespread as memory devices for high-capacity data. At present, storage elements are miniaturized for per-bit cost reduction and capacity increase, and further miniaturization in the future is demanded. However, for further miniaturization of the flash memories, there are many problems to be solved, such as the development of lithographic technology, and the inhibition of a short channel effect, inter-element interference, and inter-element variation. Therefore, it may be difficult to make future continuous improvements of storage density by simply developing in-plane miniaturization technology alone.
Accordingly, in recent years, in order to increase the degree of integration of memory cells, developments have been made to shift the structure of the memory cells from a conventional two-dimensional (planar) structure to a three-dimensional (solid) structure, and various three-dimensional nonvolatile semiconductor memory devices have been suggested. One such structure is a vertical gate (VG) type semiconductor memory structure, and this structure is characterized in that a layout including peripheral elements and others is substantially equal to the planar structure so that an active area (AA) and a gate contact (GC) that are stacked can be collectively formed.
Now, the VG type three-dimensional structure has memory cells stacked in a vertical direction that share a control gate electrode extending in the vertical direction. Thus, it becomes difficult to form the control gate electrode by a metal layer if the number of stacked layers is increased for higher integration. This is attributed to the fact that the thickness of the metal layer to be fabricated is increased by the increase of the number of stacked layers so that the fabrication of the metal layer becomes substantially impossible.
Therefore, in the VG type three-dimensional structure, the control gate electrode of the memory cell is often formed by a polysilicon layer. In addition, the control gate electrode extends in a horizontal direction as a word line. Thus, a silicide layer (low-resistance layer) for the reduction of the wiring resistance of the word line is usually provided on the upper surface of the polysilicon layer as the word line (control gate electrode). However, the distance from the silicide layer to each memory cell in each hierarchical layer varies with the memory cell. That is, the distance from the silicide layer to the uppermost memory cell via the polysilicon layer higher in resistance value than the silicide layer is shorter. In contrast, the distance from the silicide layer to the lowermost memory cell via the polysilicon layer is longer.
This leads to a situation where there is a variation of electric resistance value from the silicide layer to each memory cell. That is, the lowermost memory cell has the lowest signal transmission velocity (the highest electric resistance) as compared with the uppermost memory cell. For normal operation in all the memory cells, an operation timing has to be decided in conformity to the lowermost memory cell having the lowest signal transmission velocity. This leads to the deterioration of the performance of the whole device. This drawback becomes more significant if the number of stacked layers is increased for higher integration.